1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to transistors comprising an embedded strain-inducing semiconductor material for enhancing charge carrier mobility in a silicon-based channel region of the transistor.
2. Description of the Related Art
The fabrication of complex integrated circuits requires a large number of transistors to be formed in and on an appropriate semiconductor material. For example, several hundred million transistors and more may have to be provided in presently available complex integrated circuits, wherein performance of the transistors in the speed critical signal paths substantially determines overall performance of the integrated circuit. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. In CMOS circuits, complementary transistors, i.e., P-channel transistors and N-channel transistors, are used for forming circuit elements, such as inverters and other logic gates, to design highly complex circuit assemblies. During the fabrication of complex integrated circuits using CMOS technology, the complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor or generally a field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface positioned between highly doped drain or source regions and an inversely or weakly doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as channel length. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, has been a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
When reducing the channel length of field effect transistors, generally an increased degree of capacitive coupling is required in order to maintain controllability of the channel region, which may typically require an adaptation of a thickness and/or material composition of the gate dielectric material. For example, for a gate length of approximately 80 nm, a gate dielectric material based on silicon dioxide with a thickness of less than 2 nm may be required in high-speed transistor elements, which may, however, result in increased leakage currents caused by hot carrier injection and direct tunneling of charge carriers through the extremely thin gate dielectric material. Since a further reduction in thickness of silicon dioxide-based gate dielectric materials may increasingly become incompatible with thermal power requirements of sophisticated integrated circuits, in some approaches, the inferior controllability of the channel region of the short channel transistors caused by the continuous reduction of the critical dimensions of gate electrode structures has been addressed by an appropriate adaptation of the material composition of the gate dielectric material.
To this end, it has been proposed that, for a physically appropriate thickness of a gate dielectric material, i.e., for a thickness resulting in an acceptable level of gate leakage currents, a desired high capacitive coupling may be achieved by using appropriate material systems, which have a significantly higher dielectric constant compared to the conventionally used silicon dioxide-based materials. For example, dielectric materials including hafnium, zirconium, aluminum and the like may have a significantly higher dielectric constant and are, therefore, referred to as high-k dielectric materials, which are to be understood as materials having a dielectric constant of 10.0 or higher when measured in accordance with typical measurement techniques.
Although basically the above-identified approach is considered a very promising strategy for enhancing performance of sophisticated transistors, it turns out that the presence of the high-k dielectric material in the vicinity of the channel region may result in a pronounced degradation of charge carrier mobility, thereby at least partly offsetting the advantages gained by the increased capacitive coupling obtained by the high-k dielectric material.
It is well known that, in view of enhancing overall performance of sophisticated transistors, also various strain engineering techniques are typically applied, since creating a specific type of strain in the channel region of silicon-based transistors may result in a significant increase of the charge carrier mobility, which in turn translates into superior current drive capability and thus switching speed. A plurality of strategies have thus been developed. For instance, providing highly stressed layers above the completed transistor structures, providing strain-inducing sidewall spacer structures, embedding strain-inducing semiconductor alloys, such as silicon/germanium, silicon/carbon and the like, into drain and source areas of the transistors represent frequently used process strategies, while, in other approaches, in addition to or alternatively, also globally strained semiconductor base materials may be used.
In particular, the incorporation of a strain-inducing silicon/germanium material into the active regions of P-channel transistors is a very efficient strain-inducing mechanism, as will be described in more detail with reference to FIG. 1.
FIG. 1 schematically illustrates a cross-sectional view of a semiconductor device 100 in a manufacturing stage in which a plurality of gate electrode structures 160A, 160B, 160C are formed on an active region 102A, in and above which a plurality of P-channel transistors 150A, 150B, 150C are to be formed. The active region 102A is to be understood as a part of a silicon-based semiconductor layer 102, which in turn is formed above an appropriate substrate 101, such as a silicon substrate and the like. The semiconductor layer 102, which is initially provided in the form of a continuous semiconductor material, is appropriately laterally divided into a plurality of active regions by appropriate isolation structures (not shown), such as shallow trench isolations. As discussed above, the transistors 150A, 150B, 150C may represent highly complex semiconductor devices in which superior performance and reduced lateral dimensions are required so that the gate electrode structures 160A, 160B, 160C may be provided with a gate length of 40 nm and less, depending on the overall process and device requirements. It should be appreciated that the gate length is to be understood, according to the sectional view of FIG. 1, as the horizontal extension of a gate electrode material 163 formed on a gate dielectric material 161, which separates the electrode material 163 from a channel region 151, which in turn laterally connects to drain and source regions 152. Furthermore, the gate electrode structures 160A, 160B, 160C typically comprise a spacer structure 165. As explained above, the gate dielectric material 161 may comprise a high-k dielectric material, for instance in the form of hafnium oxide and the like, possibly in combination with a conventional silicon oxide material, silicon oxynitride material and the like, while, in other cases, a conventional silicon oxide-based dielectric material may be used as the gate dielectric layer 161. As discussed above, when a high-k dielectric material is incorporated in the layer 161, generally reduced charge carrier mobility may be induced in the channel region 151, which in turn is to be compensated for or even overcompensated by providing an additional strain-inducing mechanism.
Hence, the device 100 comprises an efficient strain-inducing mechanism on the basis of a silicon/germanium alloy 104 that is provided in respective cavities 103, which are formed in the active region 102A laterally adjacent to the respective gate electrode structures 160A, 160B, 160C. The strain-inducing effect of the silicon/germanium material 104 results from a lattice mismatch of the natural lattice constant of the silicon/germanium material compared to the silicon base material of the active region 102A. That is, upon forming the cubic face-centered crystalline structure, the germanium atomic species having a greater covalent radius compared to a silicon atom results in a greater lattice constant when the crystalline growth occurs in a non-disturbed manner. When forming the silicon/germanium crystal lattice on a silicon base material, which, thus, has a reduced lattice constant compared to the silicon/germanium alloy, the growing silicon/germanium material takes on the lattice constant of the underlying base material, thereby resulting in a deformed or strained crystalline material, which in turn may interact with the neighboring channel region 151, thereby inducing a desired compressive strain therein. Basically, the resulting strain may significantly depend on the magnitude of the lattice mismatch between the material 104 and the silicon base material of the active region 102A, wherein the actual strain in the channel region 151 is also significantly determined by the amount of strained silicon/germanium material, i.e., by the depth and shape of the cavity 103 and by the proximity of the cavity and, thus, the material 104 with respect to the channel region 151. Generally, it would, therefore, be preferable to provide the material 104 with reduced offset from the channel region 151 and with a high germanium concentration in order to increase the lattice mismatch and thus the resulting degree of lattice deformation and strain. It turns out, however, that simply increasing the germanium concentration does not necessarily result in superior transistor performance since many other aspects may also significantly contribute to the finally obtained transistor characteristics.
For example, lattice defects may occur, in particular, at the interface between the silicon base material and the strained semiconductor material 104, wherein the defect density may significantly increase with an increasing germanium concentration in the material 104. Furthermore, during the further processing, a pronounced difference in processing silicon material compared to the processing of a silicon/germanium material having a high germanium concentration may also contribute to process non-uniformities, for instance when forming a metal silicide in the drain and source regions 151, which may thus also negatively affect the final transistor characteristics.
For this reason, frequently, a “graded” germanium concentration may be used in the material 104, for instance by providing a deeper portion 104A with a moderately high germanium concentration, for instance up to 30 atomic percent or higher, while an upper portion 104B may have a significantly lower germanium concentration, for instance 20 atomic percent or less. In this manner, many disadvantages associated with a high germanium concentration at a top surface of the device 100 may be avoided or at least significantly reduced by providing the graded configuration of the silicon/germanium alloy 104.
Generally, the device 100 may be fabricated on the basis of any appropriate process strategy. For example, the active region 102A may be formed by appropriately dimensioning and forming isolation structures, which in turn is typically accomplished by applying sophisticated lithography, etch, deposition, anneal and planarization techniques. Thereafter, the basic electronic characteristics of the active region 102A are adjusted, for instance, by applying implantation processes and using an appropriate masking regime. Thereafter, the processing is continued by forming gate electrode structures, such as the structures 160A, 160B, 160C. To this end, appropriate materials are formed, for instance, by deposition techniques, wherein, as discussed above, a high-k dielectric material may be provided in combination with appropriate metal-containing electrode materials, such as titanium nitride and the like, in order to obtain a desired confinement of the sensitive high-k dielectric material and also provide an appropriate work function. To this end, it is frequently necessary to incorporate an additional metal species, such as aluminum and the like, into the metal-containing electrode material and/or into the dielectric layer 161, which may be accomplished by applying appropriate heat treatments and the like. A conventional silicon oxide-based gate dielectric is formed in combination with a polysilicon material, for instance if a negative influence of a high-k dielectric material on the charge carrier mobility is considered inappropriate. Thereafter, any further hard mask materials and cap materials are deposited as required. Next, complex lithography and etch techniques are applied in order to form the gate electrode structures 160A, 160B, 160C with the desired critical dimensions. Next, a liner material (not shown) is typically formed, for instance as a silicon nitride material, so as to confine any sensitive materials of the gate electrode structures on sidewalls thereof, followed by the formation of a portion of the spacer structure 165, which may, in other device areas, be used as a mask layer during a process sequence in which the cavities 103 may be selectively formed in the active region 102A, followed by the selective epitaxial deposition of the material 104. To this end, well-established process techniques are applied for forming the cavities 103, followed by a selective deposition sequence for forming the materials 104A, 104B. A selective epitaxial growth is performed in an ambient in which process parameters are selected in compliance with well-established process recipes so as to achieve the deposition of the silicon/germanium material on exposed crystalline silicon surface areas, while a pronounced material deposition on dielectric surface areas, such as any cap layers formed on the gate electrode structures (not shown), the spacer structures 165 and the isolation regions (not shown), is suppressed. The process parameters, such as the gas flow rate of a germanium-containing precursor gas, are appropriately adjusted in order to obtain a desired graded germanium concentration, as discussed above. Frequently, the cavities 103 are formed as box-like recesses in the active region 102A on the basis of anisotropic etch techniques. In this case, relatively steep sidewalls are formed, which may have a different crystallographic surface orientation compared to a bottom face of the cavities 103. In conventional process techniques, the process parameters of the selective epitaxial growth process are selected such that preferably a pronounced bottom-to-top fill behavior is obtained, wherein the bottom face acts as a template surface providing an increased deposition rate compared to the lateral growth rate achieved on the sidewalls of the cavities 103. In this manner, the strain-inducing material 104A may be formed so as to extend to substantially the same height throughout the entire cavity 103 and subsequently the material 104B having the reduced germanium contents may be formed so as to completely fill the respective cavity 103, wherein, if desired, an additional extra amount of silicon/germanium material of reduced germanium concentration may be formed. During the epitaxial growth of the material 104, a dopant species may be incorporated, if considered appropriate for obtaining the desired lateral and vertical profile of the drain and source regions 152. Furthermore, if required, additional dopant may be incorporated on the basis of appropriate implantation processes in order to establish the complex dopant profile. Thereafter, the spacer structure 165 may be completed and further implantation processes may be employed, if required, for incorporating further dopant species in accordance with the overall device requirements. Next, high temperature processes may be carried out in order to activate dopants and reduce implantation-induced lattice damage.
Consequently, the above described strain-inducing mechanism based on the graded strain-inducing semiconductor material 104 including the material 104A having an increased germanium concentration and the material 104B having the reduced germanium concentration is efficient so as to compensate, or even overcompensate, for any negative effect of a high-k dielectric material on the charge carrier mobility in the channel region 151, while, in other cases, performance of transistors comprising a conventional gate electrode structure may be significantly enhanced. On the other hand, upon further reducing the overall device dimensions, it turns out that increasingly a performance gain is observed that is less than expected, which is especially true in the case of sophisticated gate electrode structures, which comprise a high-k dielectric material. However, also when applying a substantially conventional approach for forming sophisticated gate electrode structures, the resulting gain in performance is less pronounced than is typically expected, thereby rendering this process strategy less attractive for future device generations requiring transistors having a critical gate length of 40 nm and less.
In view of the situation described above, the present disclosure relates to manufacturing techniques and semiconductor devices in which sophisticated transistors may be formed on the basis of an embedded strain-inducing semiconductor material, while avoiding or at least reducing the effects of one or more of the problems identified above.